The present invention generally relates to the field of polishing. In particular, the present invention is directed to a chemical mechanical polishing pad having secondary polishing medium capacity control grooves.
In the fabrication of integrated circuits and other electronic devices, multiple layers of conducting, semiconducting and dielectric materials are deposited onto and etched from a semiconductor wafer. Thin layers of these materials may be deposited by a number of deposition techniques. Common deposition techniques in modern wafer processing include physical vapor deposition (PVD) (also known as sputtering), chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD) and electrochemical plating. Common etching techniques include wet and dry isotropic and anisotropic etching, among others.
As layers of materials are sequentially deposited and etched, the surface of the wafer becomes non-planar. Because subsequent semiconductor processing (e.g., photolithography) requires the wafer to have a flat surface, the wafer needs to be periodically planarized. Planarization is useful for removing undesired surface topography as well as surface defects, such as rough surfaces, agglomerated materials, crystal lattice damage, scratches and contaminated layers or materials.
Chemical mechanical planarization, or chemical mechanical polishing (CMP), is a common technique used to planarize semiconductor wafers and other workpieces. In conventional CMP using a dual-axis rotary polisher, a wafer carrier, or polishing head, is mounted on a carrier assembly. The polishing head holds the wafer and positions it in contact with a polishing layer of a polishing pad within the polisher. The polishing pad has a diameter greater than twice the diameter of the wafer being planarized. During polishing, the polishing pad and wafer are rotated about their respective concentric centers while the wafer is engaged with the polishing layer. The rotational axis of the wafer is offset relative to the rotational axis of the polishing pad by a distance greater than the radius of the wafer such that the rotation of the pad sweeps out an annular “wafer track” on the polishing layer of the pad. When the only movement of the wafer is rotational, the width of the wafer track is equal to the diameter of the wafer. However, in some dual-axis polishers the wafer is oscillated in a plane perpendicular to its axis of rotation. In this case, the width of the wafer track is wider than the diameter of the wafer by an amount that accounts for the displacement due to the oscillation. The carrier assembly provides a controllable pressure between the wafer and polishing pad. During polishing, a slurry, or other polishing medium, is flowed onto the polishing pad and into the gap between the wafer and polishing layer. The wafer surface is polished and made planar by chemical and mechanical action of the polishing layer and polishing medium on the surface.
The interaction among polishing layers, polishing media and wafer surfaces during CMP is being increasingly studied in an effort to optimize polishing pad designs. Most of the polishing pad developments over the years have been empirical in nature. Much of the design of polishing surfaces, or layers, has focused on providing these layers with various patterns of voids and arrangements of grooves that are claimed to enhance slurry utilization and polishing uniformity. Over the years, quite a few different groove and void patterns and arrangements have been implemented. Prior art groove patterns include radial, concentric circular, Cartesian grid and spiral, among others. Prior art groove configurations include configurations wherein the width and depth of all the grooves are uniform among all grooves and configurations wherein the width or depth of the grooves varies from one groove to another.
It is noted that some pad designers have designed polishing pads that include grooves not only in the polishing surface of the pad, but also in a surface opposite the polishing pad. Such pads are described, e.g., in U.S. Patent Application Publication No. US 2004/0259479 to Sevilla. The Sevilla application discloses polishing pads for a process known as electrochemical mechanical polishing (ECMP), which is similar to CMP but also includes removing conductive material from a surface of a substrate being polished by applying an electrical bias between the polished surface and a cathode. Generally, the first set of grooves in the polishing surface of the pad are provided for the CMP portion of ECMP and the second set of grooves in the surface opposite the polishing surface facilitate the flow of an electrolyte present in the polishing medium throughout the pad. The first and second sets of grooves are oriented so that they cross each other and the individual grooves are configured so that they fluidly connect with each other where they cross. While the second set of grooves provides the pad with additional grooves, all of the grooves are active from the very first use of the pad. Consequently, as the pad wears, the overall volumetric capacity of the first and second sets of grooves decreases.
Although pad designers have devised various groove arrangements and configurations, as a conventional CMP pad wears during use, the volumetric capacity of the grooves on the pad continuously decreases. This decrease in groove capacity affects the fluid dynamics of the polishing medium in the grooves and on the polishing surface of the pad. At some point during normal wear, the effect of the decreased groove capacity on the dynamics of the polishing medium can become so great that polishing is negatively impacted. When the impact of wear on polishing becomes unacceptable, the worn pad must be discarded. Consequently, there is a need for CMP pad designs that include features that can extend the useful life of a CMP pad.